The present invention relates to a nonvolatile magnetic memory device and a manufacturing method thereof. More specifically, the present invention relates to a nonvolatile magnetic memory device called a TMR (Tunnel Magneto resistance) type MRAM (Magnetic Random Access Memory) and a manufacturing method thereof.
With great diffusion of information communication machines, particularly, personal small machines such as personal digital assistances, various semiconductor devices such as a memory, a logic and so on, constituting such machines are being demanded to cope with higher performances such as a higher degree of integration, faster operation capability and lower power consumption. Particularly, a nonvolatile memory is considered indispensable in the ubiquitous era. Even if the depletion of a power supply or some troubles occur or a server is disconnected to a network due to some failure, important information can be stored or protected with a nonvolatile memory. Further, recently available personal digital assistances are designed such that the power consumption is reduced to a lowest level possible by maintaining non-operating circuit blocks in a standby state, and the waste of power consumption and a memory can be avoided if a nonvolatile memory capable of working as a fast-speed work memory and a mass-storage memory can be realized. Further, if a fast-speed and mass-storage nonvolatile memory can be realized, the “instant-on” function of booting in the instance of turning on power can be made possible.
The nonvolatile memory includes a flash memory using a semiconductor material and a ferroelectric nonvolatile semiconductor memory (FERAM, Ferroelectric Random Access Memory) using a ferroelectric material. However, the flash memory has a defect that the writing speed is slow since it is in the order of microseconds. On the other hand, in FERAM, the number of times of re-writability thereof is 1012 to 1014, and the number cannot be said to be sufficient for replacing SRAM or DRAM with FERAM, and there is pointed out another problem that the micro-fabrication of a ferroelectric layer is difficult.
As a nonvolatile memory free of the above defects, a nonvolatile memory device called MRAM (Magnetic Random Access Memory) is in the limelight. The MRAM at an early development stage was based on a spin valve using a GMR (Giant magnetoresistance) effect. Since, however, the memory cell resistance against a load is as low as 10 to 100 Ω, the power consumption per bit on readout is large, and the defect is that it is difficult to attain the capacity of mass storage.
While the MRAM using a TMR (Tunnel Magnetoresistance) effect had a resistance change ratio of 1-2% at room temperature at an early development stage, it has come to be possible to obtain a resistance change ratio close to 20% in recent years, so that the MRAM using the TMR effect is highlighted. The TMR-type MRAM has a simple structure and enables easy scaling, and recording is made by the rotation of a magnetic moment, so that the number of times of possible re-writing is great. Further, it is expected that the TMR-type MRAM is very rapid with regard to an access time period, and it is already said that the TMR-type MRAM is capable of an operation at 100 MHz.
FIG. 40 shows a schematic partial cross-sectional view of a conventional TMR-type MRAM (to be simply referred to as “MRAM” hereinafter). The MRAM comprises a transistor for selection TR made of a MOS-type FET and a tunnel magnetoresistance device 130.
The tunnel magnetoresistance device 130 has a stacking structure constituted of a first ferromagnetic layer, a tunnel barrier 134 and a second ferromagnetic layer. More specifically, the first ferromagnetic layer has a two-layer structure, for example, of an anti-ferromagnetic layer 132 positioned below and a pinned magnetic layer 133 (called a reference layer as well) positioned above and has an intense unidirectional magnetic anisotropy due to an exchange interaction working between these two layers. The second ferromagnetic layer of which the magnetization direction rotates relatively easily is also called a free layer or memory layer 135. The tunnel barrier 134 works to cut a magnetic coupling between the memory layer 135 and the pinned magnetic layer 133 and also to flow a tunnel current. A bit line BL for connecting the MRAMs is formed on a third insulating interlayer 128. A top coating film 136 formed between the bit line BL and the memory layer 135 works to prevent mutual diffusion of atoms constituting the bit line BL and atoms constituting the memory layer 135, to reduce a contact resistance and to prevent the oxidation of the memory layer 135. In Figure, reference numeral 131 indicates a barrier layer formed between the anti-ferromagnetic layer 132 and a second insulating interlayer 125.
Further, a write-in word line RWL is arranged below the tunnel magnetoresistance device 130 through the second insulating interlayer 125. Generally, the extending direction (first direction) of the write-in word line RWL and the extending direction (second direction) of the bit line BL cross each other at right angles.
The transistor for selection TR is formed in that portion of a semiconductor substrate 110 which portion is surrounded by a device isolation region 111, and the transistor for selection TR is covered with a first insulating interlayer 121. One source/drain region 114B is connected to the barrier layer 131, the anti-ferromagnetic layer 132 and the pinned magnetic layer 133 through a first connecting hole 123 constituted of a tungsten plug, a landing pad 124 and a second connecting hole 127. That is, the second connecting hole 127 comprises extending portions of the barrier layer 131, the anti-ferromagnetic layer 132 and the pinned magnetic layer 133. The other source/drain region 114A is connected to a sense line 116 through a contact hole 115. In Figure, reference numeral 112 indicates a gate electrode, and reference numeral 113 indicates a gate insulating film.
In an MRAM array, the MRAM is arranged in an intersecting point of the bit line BL and the write-in word line RWL.
When data is written into the above-constituted MRAM, current is flowed in the bit line BL and the write-in word line RWL, to form a synthetic magnetic field, and the direction of magnetization of the second ferromagnetic layer (memory layer 135) is changed by means of the synthetic magnetic field, whereby, “1” or “0” is recorded into the second ferromagnetic layer (memory layer 135).
Data is read out by bringing the transistor for selection TR into an ON-state, flowing a current in the bit line BL and detecting a tunnel current change caused by a magnetoresistance effect with the sense line 116. When the magnetization direction of the memory layer 135 and the counterpart of the pinned magnetic layer 133 are the same, a low-resistance state results (this state represents, for example, “0”), and when the magnetization direction of the memory layer 135 and the counterpart of the pinned magnetic layer 133 are antiparallel, a high-resistance state results (this state represents, for example, “1”).
A manufacturing method of the conventional MRAM shown in FIG. 40 will be outlined below with reference to FIGS. 34A, 34B and 35 to 40 showing schematic partial cross-sectional views of the semiconductor substrate and the like.
[Step-10]
First, a MOS-type FET to work as a transistor for selection TR is formed in the semiconductor substrate 110 composed of a silicon semiconductor substrate. Then, a lower layer of the first insulating interlayer is formed on the entire surface, and then, an opening portion is formed through the lower layer of the first insulating interlayer above the source/drain region 114A by a lithography technique and an RIE method. Then, a polysilicon layer doped with an impurity is formed on the lower layer of the first insulating interlayer including an inside of the opening portion by a CVD method. Then, the polysilicon layer on the lower layer of the first insulating interlayer is patterned, whereby the sense line 116 can be formed on the lower layer of the first insulating interlayer. The sense line 116 and the source/drain region 114A are connected to each other through the contact hole 115 formed through the lower layer of the first insulating interlayer. Then, an upper layer of the first insulating interlayer is formed on the entire surface. The lower layer and the upper layer of the first insulating interlayer will be simply called “first insulating interlayer 121” all together hereinafter.
[Step-20]
Then, a first opening portion 122 is formed through the first insulating interlayer 121 above the source/drain region 114B by an RIE method, and then, the first connecting hole 123 connected to the source/drain region 114B of the transistor for selection TR is formed in the first opening portion 122.
Then, the write-in word line RWL is formed on the first insulating interlayer 121, and at the same time, the landing pad 124 is formed on the top surface of the first connecting hole 123. Then, the second insulating interlayer 125 is formed on the entire surface. In this manner, a structure shown in FIG. 34A can be obtained.
[Step-30]
Then, a resist layer 140 having an opening 141 formed above the landing pad 124 is formed on the second insulating interlayer 125 by a lithography technique (see FIG. 34B). Then, the second insulating interlayer 125 is etched with using the resist layer 140 as a mask, to form a second opening portion 126 through the second insulating interlayer 125, and then, the resist layer 140 is removed by an ashing technique. In this manner, a structure shown in FIG. 35 can be obtained. Then, for attaining excellent contact, the landing pad 124 exposed in the bottom of the second opening portion 126 is argon-sputtered.
[Step-40]
Then, the barrier layer 131, the anti-ferromagnetic layer 132, the pinned magnetic layer 133, the tunnel barrier 134, the memory layer 135 and the top coating film 136 are consecutively formed on the entire surface including an inside of the second opening portion 126. All the layers from the barrier layer 131 to the top coating film 136 are deposited on the side surface and bottom surface of the second opening portion 126 as well. In this manner, a structure shown in FIG. 36 can be obtained.
[Step-50]
Then, the top coating film 136, the memory layer 135 and the tunnel barrier 134 are patterned by a lithography technique and an RIE method, whereby the pinned magnetic layer 133, the anti-ferromagnetic layer 132 and the barrier layer 131 are allowed to remain, and further, the second connecting hole 127 formed of the extending portions of the barrier layer 131, the anti-ferromagnetic layer 132 and the pinned magnetic layer 133 can be obtained. In this manner, a structure shown in FIG. 37 can be obtained.
[Step-60]
Then, the pinned magnetic layer 133, the anti-ferromagnetic layer 132 and the barrier layer 131 are patterned (see FIG. 38), the third insulating interlayer 128 is formed on the entire surface, and then, the third insulating interlayer 128 is flattened by a CMP method, to expose the top coating film 136 (see FIG. 39). Then, the bit line BL is formed on the third insulating interlayer 128. The bit line BL is connected to the top coating film 136 and extends in the second direction (leftward and rightward on the drawing) crossing the first direction (see FIG. 40) In this case, peripheral circuits (not shown) and a bonding pad region (not shown) are formed together. Further, a silicon nitride film (not shown) is deposited on the entire surface by a plasma CVD method, and the bonding pad portion (not shown) is opened in the silicon nitride film, to complete the manufacturing process of the MRAM.
The MRAM has advantages that a higher speed and a higher integration degree can be easily accomplished as described already. However, the above process has the following problems, which will be explained below.
The second insulating interlayer 125 as a substratum for the tunnel magnetoresistance device 130 is required to have a very high flatness of several angstroms or less. The magnetization directions in the memory layer 135 and the pinned magnetic layer 133 of the tunnel magnetoresistance device 130 are required to be in parallel with the surface of the tunnel magnetoresistance device 130. However, when a convexoconcave shape exists in the surface of the second insulating interlayer 125, the memory layer 135 or the pinned magnetic layer 133 comes into a convexoconcave state, and the magnetization of the memory layer 135 or the pinned magnetic layer 133 comes to have a vertical component, so that the property of the tunnel magnetoresistance device 130 is deteriorated, or that the fluctuation of the property of the tunnel magnetoresistance device 130 is widened. Further, when a convexoconcave shape exists in the surface of the second insulating interlayer 125, the thickness of the tunnel barrier 134, which thickness is very small, as small as approximately 1 nm, varies, and the property of the tunnel magnetoresistance device 130 varies.
When the resist layer 140 on the second insulating interlayer 125 is removed in the above [Step-30], a convexoconcave shape is formed in the second insulating interlayer 125. Further, the argon sputtering treatment for the landing pad 124 forms a convexoconcave shape in the second insulating interlayer 125 as well. FIG. 35 schematically shows a state where the surface of the second insulating interlayer 125 is roughened.
Further, the second connecting hole 127 comprises the extending portions of the barrier layer 131, the anti-ferromagnetic layer 132 and the pinned magnetic layer 133. Each layer constituting the tunnel magnetoresistance device 130 has a small thickness, and a sputtering apparatus for forming each layer is specified to have high accuracy, to form a flat layer and to prevent a fluctuation of the layer thickness. Sputtering thereof is also carried out at room temperature. There is therefore caused a problem that the step coverage of the second opening portion 126 is poor as compared with the step coverage attained when a general sputtering apparatus is used, so that step cut or breakage is liable to take place in the pinned magnetic layer 133, the anti-ferromagnetic layer 132 and the barrier layer 131.